1. Field of the Invention
The present invention relates to an adaptive deadtime method and circuit implementation, particularly for use in a half bridge driver IC such as the IR-2161 Halogen Convertor Control IC described in U.S. Provisional Application Ser. No. 60/343,236 filed Dec. 31, 2001 (IR-2082 PROV), U.S. Provisional Application Ser. No. 60/398,298 filed Jul. 22, 2002 (IR-2082 PROV II) and U.S. Ser. No. 10/443,525 filed May 21, 2003 (IR-2082), each incorporated by reference.
The invention also relates to a high voltage offset detection circuit that can be incorporated along with a half-bridge gate driver circuit, particularly in a monolithic solution.
2. Related Art
A self-oscillating half bridge circuit based on bipolar power transistors or other switching power devices will be inherently efficient because the system will always be soft switching. These circuits are well known and will not be explained here. In order to achieve similar performance in a half bridge circuit where a separate oscillator drives a low and high side driver, soft switching is not inherent, so the dead time is preferably fixed to a value which corresponds to the half bridge slew time. This varies depending on the capacitances and inductances in the output circuit as well as the load current.
High voltage half-bridge driver circuits are used in various applications such as motor drives, electronic ballasts for fluorescent lamps and power supplies. The half-bridge circuits employ a pair of totem pole connected transistors that are placed across a high voltage DC power supply. The schematic in FIG. 1 shows a basic half-bridge circuit. Transistors M1 and M2 are the power devices (MOSFETS) and their midpoint connection, node “A”, is the output that is connected to the load. The transistors M1 and M2 has their own gate drive buffers (DRV1 and DRV2 respectively) which supply the proper signals to turn transistors M1 and M2 on or off.
In various applications it is of great value to know when the midpoint of the output half-bridge, node A, has transitioned from a high state to a low state or a low state to a high state. Such an application is an electronic ballast for a fluorescent lamp. A simplified schematic of such a ballast is shown in FIG. 2. As can be seen, the load on the half-bridge is a resonant circuit consisting of L1, C1 and LAMP1. During operation transistors M1 and M2 are alternatively switched on and off which causes current to build in the resonant load circuit that is connected to node A. For example: when M1 is turned on, the voltage at node A is pulled (slews) to the potential of the DC high voltage bus and current will begin to build in the resonant load. When M1 is switched off, the current flowing in the resonant load causes the voltage at node A to slew towards a lower potential. It is assumed that the switching frequency of the half-bridge is greater than the resonant frequency of the load circuit. After some “dead-time” delay, transistor M2 is turned on and the voltage at node A is pulled to the lower DC bus voltage which is typically zero potential. The dead-time delay prevents M1 and M2 from being on at the same time, which would cause a short circuit.
The slewing of the voltage at node A, prior to the turn on of M2, will take some finite amount of time to completely transition from the DC high voltage bus potential to the lower DC bus voltage. Under certain conditions the voltage at node A may not have completely transitioned to the lower potential at the time when M2 is turned on. In this case M2 will then pull the voltage at node A to the lower voltage.
This so called “hard-switching” is a source of switching loss and will cause heating of the half-bridge transistors M1 and M2, which could lead to their failure.
In order to minimize the switching losses, hard-switching can be prevented by ensuring that the voltage at node A has completely transitioned prior to the turn on of M2. This can be arranged by increasing the dead-time delay between the turn off of M1 (M2) and the turn on of M2 (M1), or by decreasing the effective capacitive loading at node A. These measures however may reduce switching speed or the available lamp rating.